Implementing Power Optimization Methodologies to Improve Energy Efficiency of Multi-Core Processors

Mohamed Azard Rilvan, Shervin Hajiamini, Lauren Hiland


Chip multi-core processors consume a large portion of system’s total power. A core contains periods of internal computation and communication during an execution of an application. In the periods of communication, core requests data from the memory during which it remains in an idle state until it receives the requested data. The waiting time of the cores provide an opportunity to save energy by reducing the voltage and frequency at the cost of performance degradation. Dynamic voltage and frequency scaling (DVFS) is a technique that predicts voltage and frequency based on the computation and communication characteristics of a running application on the multi-core system. We integrate a history-based DVFS methodology with Gem 5, a full system cycle accurate simulator, to investigate the maximum energy efficiency gained by this methodology for various computation and communication intensive applications. We measure the intensity of CPU-bound and memory-bound portions of the applications periodically during the runtime. The CPU-bound portions are the busy utilizations of the processor cores, and the memory bound portions are the utilization of the memory, that is the amount of the data requests the memory receives from the CPUs (cores). We aim to compute the prediction accuracy, which is the tracking distance between the voltage and frequency (predicted by the methodology) and the actual CPU-bound/memory-bound intensity of a program in each time period. We compare the proposed history-based DVFS methodology with a simple history based DVFS methodology. The latter adjusts the voltage and frequency solely based on the core’s busy utilization for the past few time periods, while our proposed DVFS methodology adjusts voltage and frequency based on the core’s busy utilization as well as the memory utilization for the current and past few time periods. We evaluate these methodologies in terms of energy savings (energy reduction) and execution time penalty (performance degradation) compared to the non-DVFS setup.


Dynamic voltage and frequency (DVFS), history based DVFS, CPU and memory bound operations

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