Analytical Delay and Variations Modeling in the Subthreshold Region

Sungil Kim


Power constraint on modern electronics has been an increasingly significant part of VLSI design. Thus, subthreshold circuit design where the supply voltage is less than the device threshold voltage gained renewed attention to reduce the energy. However, such reduction comes with process, voltage, and temperature (PVT) variations. Furthermore, as previous analytical delay models (i.e. Alpha-power law MOSFET model) do not take account of these variations, their errors in subthreshold region are large.  Therefore, this paper presents analytical delay model that considers PVT variations and models variations of analytical delay in the subthreshold region. The proposed model is verified through the simulation on PTM low power 16-nm technology (threshold voltage = 0.68V). Result shows that the proposed analytical delay model has a maximum error of 33.4% while Alpha-power law MOSFET model has a maximum error of 71.1% for 0 to 1 input transition over the range of 0.2V to 0.4V of supply voltage. In addition, three analytical delay variations are modeled and verified. In contrast to previous research, the proposed model considers the drain-induced barrier lowering (DIBL) effect. The accuracy is improved with a compensation factor and verified for the range of 0.15V to 0.4V of supply voltage along with threshold voltage variation up to 30mV, supply voltage variation up to 50mV, and temperature variation up to 20oC. By considering process variations, supply voltage, and temperature variations, we demonstrate the delay variations up to 4.31. Result shows an average error of 1%, 14.6%, and 6.8% for PVT variations respectively. These results can further the applicability of subthreshold circuit for ultra-low-power electronics.


Analytical Delay Model, Subthreshold Circuits, PVT Variations

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