Optimization of Reactive Ion Etching (RIE) Parameters for Selective Removal of MOSFET Gate Dielectric and Evaluation of its Physical and Electrical Properties

Hojoon Lee, Samuel C. Wood

Abstract


The integrated circuit (IC) is dominated by technology using Complementary Metal-oxide-Semiconductor Field- effect Transistor (CMOSFET). In order to put few hundred millions of transistors on silicon chip requires selective removal of material by Reactive Ion Etching (RIE) which ensures vertical cut thereby increasing packing density of devices on the chip. The gate insulator of CMOS devices plays a crucial role in its electrical performance. In this research gate insulator of MOSFET has been etched by state-of-art technique RIE and its physical and electrical properties have been measured. The gate insulator etching by RIE give rise to charge accumulation on the gate dielectric resulting in change in threshold voltage. Also early breakdown of MOS devices is a direct consequence of charge accumulation on gate dielectric during RIE process. The RIE etching was performed with Technics Series 85-RIE unit, and it was optimized in respect of power, pressure, and composition of gases to achieve less charge accumulation, and stable threshold voltage. The thickness of the gate insulator was measured by the Nanospec before and after etching. Charges accumulated on gate oxide were measured by HP 4280A which is a high frequency capacitance-voltage (CV) measurement system. Annealing of the RIE etched gate oxide were performed at suitable temperature to bring the charges to minimum level. Results of the research are presented in tables and figures.


Keywords


RIE; Gate dielectric; Oxide trapped charges

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